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HI-574A, HI-674A
TM
Data Sheet
June 2001
File Number
3096.5
Complete, 12-Bit A/D Converters with Microprocessor Interface itle I4A, 4A, 4) bjec omp e, -Bit D nver s th crop esso erfa utho ) eyw s tersi rpor on, ico ucto /D, C, sh, nver , bit, le dem
The HI-X74(A) is a complete 12-bit, Analog-to-Digital Converter, including a +10V reference clock, three-state outputs and a digital interface for microprocessor control. Successive approximation conversion is performed by two monolithic dice housed in a 28 lead package. The bipolar analog die features the Intersil Dielectric Isolation process, which provides enhanced AC performance and freedom from latch-up. Custom design of each IC (bipolar analog and CMOS digital) has yielded improved performance over existing versions of this converter. The voltage comparator features high PSRR plus a high speed current-mode latch, and provides precise decisions down to 0.1 LSB of input overdrive. More than 2X reduction in noise has been achieved by using current instead of voltage for transmission of all signals between the analog and digital ICs. Also, the clock oscillator is current controlled for excellent stability over temperature. The HI-X74(A) offers standard unipolar and bipolar input ranges, laser trimmed for specified linearity, gain and offset accuracy. The low noise buried zener reference circuit is trimmed for minimum temperature coefficient. Power requirements are +5V and 12V to 15V, with typical dissipation of 385mW (HI-574A/674A) at 12V.
Features
* Complete 12-Bit A/D Converter with Reference and Clock * Full 8-Bit, 12-Bit or 16-Bit Microprocessor Bus Interface * Bus Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns * No Missing Codes Over Temperature * Minimal Setup Time for Control Signals * Fast Conversion Times - HI-574A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25s - HI-674A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15s * Low Noise, via Current-Mode Signal Transmission Between Chips * Byte Enable/Short Cycle (AO Input) - Guaranteed Break-Before-Make Action, Eliminating Bus Contention During Read Operation. Latched by Start Convert Input (To Set the Conversion Length) * Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 12V to 15V
Applications
* Military and Industrial Data Acquisition Systems * Electronic Test and Scientific Instrumentation * Process Control Systems
Pinout
(PDIP, SBDIP) TOP VIEW
+5V SUPPLY, VLOGIC DATA MODE SEL, 12/8 CHIP SEL, CS BYTE ADDR/SHORT CYCLE, AO READ/CONVERT, R/C CHIP ENABLE, CE +12V/+15V SUPPLY, VCC +10V REF, REF OUT ANALOG COMMON, AC 1 2 3 4 5 6 7 8 9 28 STATUS, STS 27 DB11 26 DB10 25 DB9 24 DB8 23 DB7 22 DB6 21 DB5 20 DB4 19 DB3 18 DB2 17 DB1 16 DB0 LSB DIGITAL DATA OUTPUTS MSB
REFERENCE INPUT 10 -12V/-15V SUPPLY, VEE 11 BIPOLAR OFFSET 12 BIP OFF 10V INPUT 13 20V INPUT 14
15 DIG COMMON, DC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright (c) Intersil Americas Inc. 2001
HI-574A, HI-674A Ordering Information
PART NUMBER HI3-574AJN-5 HI3-574AKN-5 HI1-574AJD-5 HI1-574AKD-5 HI1-574ASD-2 HI1-574ATD-2 HI1-574ASD/883 HI1-574ATD/883 HI3-674AJN-5 HI3-674AKN-5 HI1-674AJD-5 HI1-674AKD-5 HI1-674ASD-2 HI1-674ATD/883 INL 1.0 LSB 0.5 LSB 1.0 LSB 0.5 LSB 1.0 LSB 0.5 LSB 1.0 LSB 0.5 LSB 1.0 LSB 0.5 LSB 1.0 LSB 0.5 LSB 1.0 LSB 0.5 LSB TEMPERATURE RANGE (oC) 0 to 75 0 to 75 0 to 75 0 to 75 -55 to 125 -55 to 125 -55 to 125 -55 to 125 0 to 75 0 to 75 0 to 75 0 to 75 -55 to 125 -55 to 125 PACKAGE 28 Ld PDIP 28 Ld PDIP 28 Ld SBDIP 28 Ld SBDIP 28 Ld SBDIP 28 Ld SBDIP 28 Ld SBDIP 28 Ld SBDIP 28 Ld PDIP 28 Ld PDIP 28 Ld SBDIP 28 Ld SBDIP 28 Ld SBDIP 28 Ld SBDIP PKG. NO. E28.6 E28.6 D28.6 D28.6 D28.6 D28.6 D28.6 D28.6 E28.6 E28.6 D28.6 D28.6 D28.6 D28.6
Functional Block Diagram
BIT OUTPUTS MSB LSB
12/8 CS AO R/C CE CONTROL LOGIC
NIBBLE A (NOTE)
NIBBLE B (NOTE)
NIBBLE C (NOTE)
THREE-STATE BUFFERS AND CONTROL VLOGIC POWER-UP RESET 12 BITS DIGITAL COMMON STS
CLK OSCILLATOR
SAR
STROBE DIGITAL CHIP ANALOG CHIP 12 BITS
VCC VEE
VREF IN 10K VREF OUT
DAC
COMP
-
+
5K +10V REF +
-
5K
10K 5K
2.5K
ANALOG COMMON
BIP OFF
20V 10V INPUT INPUT
NOTE: "Nibble" is a 4-bit digital word.
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HI-574A, HI-674A
Absolute Maximum Ratings
Supply Voltage VCC to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +16.5V VEE to Digital Common . . . . . . . . . . . . . . . . . . . . . . . 0V to -16.5V VLOGIC to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +7V Analog Common to Digital Common. . . . . . . . . . . . . . . . . . . . . . 1V Control Inputs (CE, CS, AO, 12/8, R/C) to Digital Common . . -0.5V to VLOGIC +0.5V Analog Inputs (REFIN, BIPOFF, 10VIN) to Analog Common . . . . . . . . . . 16.5V 20VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . . . . . 24V REFOUT . . . . . Indefinite Short To Common, Momentary Short To VCC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC ( oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . 55 18 PDIP Package . . . . . . . . . . . . . . . . . . . 60 N/A Maximum Junction Temperature PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Die Characteristics Operating Conditions
Temperature Range HI3-574Axx-5, HI1-674Axx-5 . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI1-574AxD-2, HI1-674AxD-2 . . . . . . . . . . . . . . . -55oC to 125oC Transistor Count HI-574A, HI-674A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1117
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC and Transfer Accuracy Specifications Typical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified TEMPERATURE RANGE -5 (0oC to 75oC) PARAMETER DYNAMIC CHARACTERISTICS Resolution (Max) Linearity Error 25oC (Max) 0oC to 75oC (Max) Max Resolution For Which No Missing Codes Is Guaranteed 25oC TMIN to TMAX Unipolar Offset (Max) Adjustable to Zero Bipolar Offset (Max) VIN = 0V (Adjustable to Zero) VIN = -10V Full Scale Calibration Error 25oC (Max), With Fixed 50 Resistor From REF OUT To REF IN (Adjustable to Zero) TMIN to TMAX (No Adjustment At 25oC) TMIN to TMAX (With Adjustment To Zero 25oC) Temperature Coefficients Guaranteed Max Change, TMIN to TMAX (Using Internal Reference) Unipolar Offset Bipolar Offset Full Scale Calibration 2 2 9 1 1 2 LSB LSB LSB 0.25 0.475 0.22 0.25 0.375 0.12 % of FS % of FS % of FS 4 0.15 4 0.1 LSB % of FS 2 1.5 LSB 12 11 12 12 Bits Bits 1 1 1/2 1/2 LSB LSB 12 12 Bits J SUFFIX K SUFFIX UNITS
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HI-574A, HI-674A
DC and Transfer Accuracy Specifications Typical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified (Continued) TEMPERATURE RANGE -5 (0oC to 75oC) PARAMETER Power Supply Rejection Max Change In Full Scale Calibration +13.5V < VCC < +16.5V or +11.4V < VCC < +12.6V +4.5V < VLOGIC < +5.5V -16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V ANALOG INPUTS Input Ranges Bipolar -5 to +5 (Note 3) -10 to +10 (Note 4) Unipolar 0 to +10 (Note 3) 0 to +20 (Note 4) Input Impedance 10V Span 20V Span POWER SUPPLIES Operating Voltage Range VLOGIC VCC VEE Operating Current ILOGIC ICC +15V Supply IEE -15V Supply Power Dissipation 15V, +5V 12V, +5V Internal Reference Voltage TMIN to TMAX Output Current, Available For External Loads (External Load Should Not Change During Conversion).
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J SUFFIX
K SUFFIX
UNITS
2 1/2 2
1 1/2 1
LSB LSB LSB
V V V V
5K, 25% 10K, 25%

+4.5 to +5.5 +11.4 to +16.5 -11.4 to -16.5
V V V
7 Typ, 15 Max 11 Typ, 15 Max 21 Typ, 28 Max
mA mA mA
515 Typ, 720 Max 385 Typ
mW mW
+10.00 0.05 Max 2.0 Max
V mA
DC and Transfer Accuracy SpecificationsTypical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified (Continued) TEMPERATURE RANGE -2 (-55oC to 125oC) PARAMETER DYNAMIC CHARACTERISTICS Resolution (Max) 12 12 Bits S SUFFIX T SUFFIX UNITS
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HI-574A, HI-674A
DC and Transfer Accuracy SpecificationsTypical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified (Continued) TEMPERATURE RANGE -2 (-55oC to 125oC) PARAMETER Linearity Error 25oC -55oC to 125oC (Max) Max Resolution For Which No Missing Codes Is Guaranteed 25oC TMIN to TMAX Unipolar Offset (Max) Adjustable to Zero Bipolar Offset (Max) VIN = 0V (Adjustable to Zero) VIN = -10V Full Scale Calibration Error 25oC (Max), With Fixed 50 Resistor From REF OUT To REF IN (Adjustable To Zero) TMIN to TMAX (No Adjustment At 25oC) TMIN to TMAX (With Adjustment To Zero At 25oC) Temperature Coefficients Guaranteed Max Change, TMIN to TMAX (Using Internal Reference) Unipolar Offset Bipolar Offset Full Scale Calibration Power Supply Rejection Max Change In Full Scale Calibration +13.5V < VCC < +16.5V or +11.4V < VCC < +12.6V +4.5V < VLOGIC < +5.5V -16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V ANALOG INPUTS Input Ranges Bipolar -5 to +5 (Note 3) -10 to +10 (Note 4) Unipolar 0 to +10 (Note 3) 0 to +20 (Note 4) Input Impedance 10V Span 20V Span POWER SUPPLIES Operating Voltage Range VLOGIC VCC VEE +4.5 to +5.5 +11.4 to +16.5 -11.4 to -16.5 V V V 5K, 25% 10K, 25% V V V V 2 1/2 2 1 1/2 1 LSB LSB LSB 2 2 20 1 2 10 LSB LSB LSB 0.25 0.75 0.50 0.25 0.50 0.25 % of FS % of FS % of FS 4 0.15 4 0.1 LSB % of FS 2 1.5 LSB 12 11 12 12 Bits Bits 1 1 1/2 1 LSB LSB S SUFFIX T SUFFIX UNITS
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HI-574A, HI-674A
DC and Transfer Accuracy SpecificationsTypical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified (Continued) TEMPERATURE RANGE -2 (-55oC to 125oC) PARAMETER Operating Current ILOGIC ICC +15V Supply IEE -15V Supply Power Dissipation 15V, +5V 12V, +5V Internal Reference Voltage TMIN to TMAX Output current, available for external loads (external load should not change during conversion). +10.00 0.05 Max 2.0 Max V mA 515 Typ, 720 Max 385 Typ mW mW 7 Typ, 15 Max 11 Typ, 15 Max 21 Typ, 28 Max mA mA mA S SUFFIX T SUFFIX UNITS
Digital Specifications All Models, Over Full Temperature Range
PARAMETER Logic Inputs (CE, CS, R/C, AO,12/8) Logic "1" Logic "0" Current Capacitance Logic Outputs (DB11-DB0, STS) Logic "0" (ISINK - 1.6mA) Logic "1" (ISOURCE - 500A) Logic "1" (ISOURCE - 10A) Leakage (High-Z State, DB11-DB0 Only) Capacitance +2.4V +4.5V 0.1A 5pF +0.4V 5A +2.4V -0.5V 0.1A 5pF +5.5V +0.8V 5A MIN TYP MAX
Timing Specifications (HI-574A) 25oC, Note 2, Unless Otherwise Specified
SYMBOL CONVERT MODE tDSC tHEC tSSC tHSC tSRC tHRC tSAC tHAC tC STS Delay from CE CE Pulse Width CS to CE Setup CS Low During CE High R/C to CE Setup R/C Low During CE High AO to CE Setup AO Valid During CE High Conversion Time 12-Bit Cycle TMIN to TMAX 8-Bit Cycle TMIN to TMAX 50 50 50 50 50 0 50 15 10 20 13 200 25 17 ns ns ns ns ns ns ns ns s s PARAMETER MIN TYP MAX UNITS
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HI-574A, HI-674A
Timing Specifications (HI-574A) 25oC, Note 2, Unless Otherwise Specified (Continued)
SYMBOL READ MODE tDD tHD tHL tSSR tSRR tSAR tHSR tHRR tHAR tHS Access Time from CE Data Valid After CE Low Output Float Delay CS to CE Setup R/C to CE Setup AO to CE Setup CS Valid After CE Low R/C High After CE Low AO Valid After CE Low STS Delay After Data Valid 25 50 0 50 0 0 50 300 75 100 150 150 1200 ns ns ns ns ns ns ns ns ns ns PARAMETER MIN TYP MAX UNITS
Timing Specifications (HI-674A) 25oC, Note 2, Unless Otherwise Specified
SYMBOL CONVERT MODE tDSC tHEC tSSC tHSC tSRC tHRC tSAC tHAC tC STS Delay from CE CE Pulse Width CS to CE Setup CS Low During CE High R/C to CE Setup R/C Low During CE High AO to CE Setup AO Valid During CE High Conversion Time 12-Bit Cycle TMIN to TMAX 8-Bit Cycle TMIN to TMAX READ MODE tDD tHD tHL tSSR tSRR tSAR tHSR tHRR tHAR tHS NOTES: 2. Time is measured from 50% level of digital transitions. Tested with a 50pF and 3k load. 3. For the "10V Input", Pin 13. 4. For the "20V Input", Pin 14. Access Time from CE Data Valid After CE Low Output Float Delay CS to CE Setup R/C to CE Setup AO to CE Setup CS Valid After CE Low R/C High After CE Low AO Valid After CE Low STS Delay After Data Valid 25 50 0 50 0 0 50 25 75 100 150 150 850 ns ns ns ns ns ns ns ns ns ns 50 50 50 50 50 0 50 9 6 12 8 200 15 10 ns ns ns ns ns ns ns ns s s PARAMETER MIN TYP MAX UNITS
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HI-574A, HI-674A Pin Descriptions
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SYMBOL VLOGIC 12/8 CS AO R/C CE VCC REF OUT AC REF IN VEE BIP OFF 10V Input 20V Input DC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 STS DESCRIPTION Logic supply pin (+5V) Data Mode Select - Selects between 12bit and 8-bit output modes. Chip Select - Chip Select high disables the device. Byte Address/Short Cycle - See Table 1 for operation. Read/Convert - See Table 1 for operation. Chip Enable - Chip Enable low disables the device. Positive Supply (+12V/+15V) +10V Reference Analog Common Reference Input Negative Supply (-12V/-15V). Bipolar Offset 10V Input - Used for 0V to 10V and -5V to +5V input ranges. 20V Input - Used for 0V to 20V and -10V to +10V input ranges. Digital Common Data Bit 0 (LSB) Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 8 Data Bit 9 Data Bit 10 Data Bit 11 (MSB) Status Bit - Status high implies a conversion is in progress.
The HI-X74AK grade is guaranteed for maximum nonlinearity of 1/2 LSB. For this grade, this means that an analog value which falls exactly in the center of a given code width will result in the correct digital output code. Values nearer the upper or lower transition of the code width may produce the next upper or lower digital output code. The HI-X74AJ is guaranteed to 1 LSB max error. For this grade, an analog value which falls within a given code width will result in either the correct code for that region or either adjacent one. Note that the linearity error is not user-adjustable.
Differential Linearity Error (No Missing Codes)
A specification which guarantees no missing codes requires that every code combination appear in a monotonic increasing sequence as the analog input level is increased. Thus every code must have a finite width. For the HI-X74AK grade, which guarantees no missing codes to 12-bit resolution, all 4096 codes must be present over the entire operating temperature ranges. The HI-X74AJ grade guarantees no missing codes to 11-bit resolution over temperature; this means that all code combinations of the upper 11 bits must be present; in practice very few of the 12bit codes are missing.
Unipolar Offset
The first transition should occur at a level 1/2 LSB above analog common. Unipolar offset is defined as the deviation of the actual transition from that point. This offset can be adjusted as discussed on the following pages. The unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with or without external adjustment.
Bipolar Offset
Similarly, in the bipolar mode, the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 LSB below analog common. The bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature.
Full Scale Calibration Error
The last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 11/2 LSB below the nominal full scale (9.9963V for 10.000V full scale). The full scale calibration error is the deviation of the actual level at the last transition from the ideal level. This error, which is typically 0.05 to 0.1% of full scale, can be trimmed out as shown in Figures 2 and 3. The full scale calibration error over temperature is given with and without the initial error trimmed out. The temperature coefficients for each grade indicate the maximum change in the full scale gain from the initial value using the internal 10V reference.
Definitions of Specifications
Linearity Error
Linearity error refers to the deviation of each individual code from a line drawn from "zero" through "full scale". The point used as "zero" occurs 1/2 LSB (1.22mV for 10V span) before the first code transition (all zeros to only the LSB "on"). "Full scale" is defined as a level 11/2 LSB beyond the last code transition (to all ones). The deviation of a code from the true straight line is measured from the middle of each particular code.
Temperature Coefficients
The temperature coefficients for full-scale calibration, unipolar offset, and bipolar offset specify the maximum
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HI-574A, HI-674A
change from the initial (25oC) value to the value at TMIN or TMAX .
Power Supplies
Supply voltages to the HI-X74A (+15V, -15V and +5V) must be "quiet" and well regulated. Voltage spikes on these lines can affect the converter's accuracy, causing several LSBs to flicker when a constant input is applied. Digital noise and spikes from a switching power supply are especially troublesome. If switching supplies must be used, outputs should be carefully filtered to assure "quiet" DC voltage at the converter terminals. Further, a bypass capacitor pair on each supply voltage terminal is necessary to counter the effect of variations in supply current. Connect one pair from pin 1 to 15 (VLOGIC supply), one from pin 7 to 9 (V CC to Analog Common) and one from pin 11 to 9 (VEE to Analog Common). For each capacitor pair, a 10F tantalum type in parallel with a 0.1F ceramic type is recommended.
Power Supply Rejection
The standard specifications for the HI-X74A assume use of +5.00V and 15.00V or 12.00V supplies. The only effect of power supply error on the performance of the device will be a small change in the full scale calibration. This will result in a linear change in all lower order codes. The specifications show the maximum change in calibration from the initial value with the supplies at the various limits.
Code Width
A fundamental quantity for A/D converter specifications is the code width. This is defined as the range of analog input values for which a given digital output code will occur. The nominal value of a code width is equivalent to 1 least significant bit (LSB) of the full scale range or 2.44mV out of 10V for a 12-bit ADC.
Ground Connections
Pins 9 and 15 should be tied together at the package to guarantee specified performance for the converter. In addition, a wide PC trace should run directly from pin 9 to (usually) +15V common, and from pin 15 to (usually) the +5V Logic Common. If the converter is located some distance from the system's "single point" ground, make only these connections to pins 9 and 15: Tie them together at the package, and back to the system ground with a single path. This path should have low resistance. (Code dependent currents flow in the VCC , VEE and VLOGIC terminals, but not through the HI-X74A's Analog Common or Digital Common).
Quantization Uncertainty
Analog-to-digital converters exhibit an inherent quantization uncertainty of 1/2 LSB. This uncertainty is a fundamental characteristic of the quantization process and cannot be reduced for a converter of given resolution.
Left-Justified Data
The data format used in the HI-X74A is left-justified. This means that the data represents the analog input as a fraction of full-scale, ranging from 0 to 4095 . This implies a 4096 binary point to the left of the MSB.
Analog Signal Source
HI-574A and HI-674A
The device chosen to drive the HI-X74A analog input will see a nominal load of 5k (10V range) or 10k (20V range). However, the other end of these input resistors may change 400mV with each bit decision, creating abrupt changes in current at the analog input. Thus, the signal source must maintain its output voltage while furnishing these step changes in load current, which occur at 1.6s and 950ns intervals for the HI-574A and HI-674A, respectively. This requires low output impedance and fast settling by the signal source. The output impedance of an op amp, for example, has an open loop value which, in a closed loop, is divided by the loop gain available at a frequency of interest. The amplifier should have acceptable loop gain at 600kHz for use with the HI-X74A. To check whether the output properties of a signal source are suitable, monitor the HI-X74A's input (pin 13 or 14) with an oscilloscope while a conversion is in progress. Each of the twelve disturbances should subside in 1s or less for the HI-574A and 500ns or less for the HI-674A. (The comparator decision is made about 1.5s and 850ns after each code change from the SAR for the HI-574A and HI-674A, respectively.) If the application calls for a Sample/Hold to precede the converter, it should be noted that not all Sample/Holds are compatible with the HI-574A in the manner described above.
Applying the HI-X74A
For each application of this converter, the ground connections, power supply bypassing, analog signal source, digital timing and signal routing on the circuit board must be optimized to assure maximum performance. These areas are reviewed in the following sections, along with basic operating modes and calibration requirements.
Physical Mounting and Layout Considerations
LAYOUT Unwanted, parasitic circuit components, (L, R, and C) can make 12-bit accuracy impossible, even with a perfect A/D converter. The best policy is to eliminate or minimize these parasitics through proper circuit layout, rather than try to quantify their effects. The recommended construction is a double-sided printed circuit board with a ground plane on the component side. Other techniques, such as wire-wrapping or point-to-point wiring on vector board, will have an unpredictable effect on accuracy. In general, sensitive analog signals should be routed between ground traces and kept well away from digital lines. If analog and digital lines must cross, they should do so at right angles.
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HI-574A, HI-674A
These will require an additional wideband buffer amplifier to lower their output impedance. A simpler solution is to use the Intersil HA-5320 Sample/Hold, which was designed for use with the HI-574A.
2 12/8 3 CS STS 28 HIGH BITS 24-27 MIDDLE BITS 20-23 5 R/C LOW BITS +15V GAIN R2 100K 10 REF IN 100 8 REF OUT 100 12 BIP OFF 0V TO +10V ANALOG INPUTS 0V TO +20V 9 ANA COM DIG COM 15 13 10VIN 14 20VIN +15V 7 -15V 11 +5V 1 6 CE 16-19
Range Connections and Calibration Procedures
The HI-X74A is a "complete" A/D converter, meaning it is fully operational with addition of the power supply voltages, a Start Convert signal, and a few external components as shown in Figure 2 and Figure 3. Nothing more is required for most applications. Whether controlled by a processor or operating in the standalone mode, the HI-X74A offers four standard input ranges: 0V to +10V, 0V to +20V, 5V and 10V. The maximum errors for gain and offset are listed under Specifications. If required, however, these errors may be adjusted to zero as explained below. Power supply and ground connections have been discussed in an earlier section.
4 AO OFFSET R1 100K -15V
Unipolar Connections and Calibration
Refer to Figure 2. The resistors shown (see Note below) are for calibration of offset and gain. If this is not required, replace R2 with a 50, 1% metal film resistor and remove the network on pin 12. Connect pin 12 to pin 9. Then, connect the analog signal to pin 13 for the 0V to 10V range, or to pin 14 for the 0V to 20V range. Inputs to +20V (5V over the power supply) are no problem - the converter operates normally. Calibration consists of adjusting the converter's most negative output to its ideal value (offset adjustment), then, adjusting the most positive output to its ideal value (gain adjustment). To understand the procedure, note that in principle, one is setting the output with respect to the midpoint of an increment of analog input, as denoted by two adjacent code changes. Nominal value of an increment is one LSB. However, this approach is impractical because nothing "happens" at a midpoint to indicate that an adjustment is complete. Therefore, calibration is performed in terms of the observable code changes instead of the midpoint between code changes. For example, midpoint of the first LSB increment should be positioned at the origin, with an output code of all 0's. To do this, apply an input of +1/2 LSB (+1.22mV for the 10V range; +2.44mV for the 20V range). Adjust the Offset potentiometer R1 until the first code transition flickers between 0000 0000 0000 and 0000 0000 0001. Next, perform a Gain Adjust at positive full scale. Again, the ideal input corresponding to the last code change is applied. This is 11/2 LSBs below the nominal full scale (+9.9963V for 10V range; +19.9927V for 20V range). Adjust the Gain potentiometer R2 for flicker between codes 1111 1111 1110 and 1111 1111 1111.
When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 1. UNIPOLAR CONNECTIONS
2 12/8 3 CS 4 AO 5 R/C
STS 28 HIGH BITS 24-27 MIDDLE BITS 20-23 LOW BITS
GAIN R2
6 CE
16-19
10 REF IN 100 8 REF OUT 100 5V ANALOG INPUTS 10V 9 ANA COM DIG COM 15 R1 OFFSET 12 BIP OFF +5V 1 +15V 7 -15V 11
13 10VIN 14 20VIN
When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 2. BIPOLAR CONNECTIONS
Bipolar Connections and Calibration
Refer to Figure 3. The gain and offset errors listed under Specifications may be adjusted to zero using potentiometers R1 and R2 (see Note below). If this isn't required, either or both pots may be replaced by a 50, 1% metal film resistor.
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HI-574A, HI-674A
Connect the Analog signal to pin 13 for a 5V range, or to pin 14 for a 10V range. Calibration of offset and gain is similar to that for the unipolar ranges as discussed above. First apply a DC input voltage 1/2 LSB above negative full scale (i.e., -4.9988V for the 5V range, or -9.9976V for the 10V range). Adjust the offset potentiometer R1 for flicker between output codes 0000 0000 0000 and 0000 0000 0001. Next, apply a DC input voltage 11/2 LSBs below positive full scale (+4.9963V for 5V range; +9.9927V for 10V range). Adjust the Gain potentiometer R2 for flicker between codes 1111 1111 1110 and 1111 1111 1111.
NOTE: The 100 potentiometer R2 provides Gain Adjust for the 10V and 20V ranges. In some applications, a full scale of 10.24V (LSB equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more convenient. For these, replace R2 by a 50, 1% metal film resistor. Then, to provide Gain Adjust for the 10.24V range, add a 200 potentiometer in series with pin 13. For the 20.48V range, add a 500 potentiometer in series with pin 14. HI-574A STAND-ALONE MODE TIMING SYMBOL PARAMETER MIN TYP MAX UNITS
Time is measured from 50% level of digital transitions. Tested with a 50pF and 3k load. HI-674A STAND-ALONE MODE TIMING SYMBOL tHRL tDS tHDR tHS tHRH tDDR PARAMETER Low R/C Pulse Width STS Delay from R/C Data Valid after R/C Low STS Delay after Data Valid High R/C Pulse Width Data Access Time MIN 50 25 25 150 TYP MAX UNITS 200 850 150 ns ns ns ns ns ns
Controlling the HI-X74A
The HI-X74A includes logic for direct interface to most microprocessor systems. The processor may take full control of each conversion, or the converter may operate in the "stand-alone" mode, controlled only by the R/C input. Full control consists of selecting an 8-bit or 12-bit conversion cycle, initiating the conversion, and reading the output data when ready-choosing either 12 bits at once or 8 followed by 4, in a left-justified format. The five control inputs are all TTL/CMOS-compatible: (12/8, CS, AO , R/C and CE). Table 1 illustrates the use of these inputs in controlling the converter's operations. Also, a simplified schematic of the internal control logic is shown in Figure 7.
Time is measured from 50% level of digital transitions. Tested with a 50pF and 3k load.
Conversion Length A Convert Start transition (see Table 1) latches the state of AO , which determines whether the conversion continues for 12 bits (AO low) or stops with 8 bits (AO high). If all 12 bits are read following an 8-bit conversion, the last three LSBs will read ZERO and DB3 will read ONE. AO is latched because it is also involved in enabling the output buffers (see "Reading the Output Data"). No other control inputs are latched.
TABLE 1. TRUTH TABLE FOR HI-X74A CONTROL INPUTS CE 0 X 1 1 1 1 1 1 1 CS X 1 0 0 0 0 0 0 0 R/C X X 0 0 0 0 1 1 1 12/8 X X X X X X X X 1 0 0 AO X X 0 1 0 1 0 1 X 0 1 None None Initiate 12-bit conversion Initiate 8-bit conversion Initiate 12-bit conversion Initiate 8-bit conversion Initiate 12-bit conversion Initiate 8-bit conversion Enable 12-bit Output Enable 8 MSBs Only Enable 4 LSBs Plus 4 Trailing Zeroes OPERATION
"Stand-Alone Operation"
The simplest control interface calls for a single control line connected to R/C. Also, CE and 12/8 are wired high, CS and AO are wired low, and the output data appears in words of 12 bits each. The R/C signal may have any duty cycle within (and including) the extremes shown in Figures 8 and 9. In general, data may be read when R/C is high unless STS is also high, indicating a conversion is in progress. Timing parameters particular to this mode of operation are listed below under "Stand-Alone Mode Timing".
HI-574A STAND-ALONE MODE TIMING SYMBOL tHRL tDS tHDR tHS tHRH tDDR PARAMETER Low R/C Pulse Width STS Delay from R/C Data Valid after R/C Low STS Delay after Data Valid High R/C Pulse Width Data Access Time MIN 50 25 300 150 TYP MAX UNITS 200 1200 150 ns ns ns ns ns ns
Conversion Start
A conversion may be initiated as shown in Table 1 by a logic transition on any of three inputs: CE, CS or R/C. The last of the three to reach the correct state starts the conversion, so one, two or all three may be dynamically controlled. The nominal delay from each is the same, and if necessary, all three may change state simultaneously. However, to ensure
11
HI-574A, HI-674A
that a particular input controls the start of conversion, the other two should be set up at least 50ns earlier. See the HI-X74A Timing Specifications, Convert Mode. This variety of HI-X74A control modes allows a simple interface in most system applications. The Convert Start timing relationships are illustrated in Figure 4. The output signal STS indicates status of the converter by going high only while a conversion is in progress. While STS is high, the output buffers remain in a high impedance state and data cannot be read. Also, an additional Start Convert will not reset the converter or reinitiate a conversion while STS is high. With 12/8 low, the output is organized in two 8-bit bytes, selected one at a time by AO . This allows an 8-bit data bus to be connected as shown in Figure 6. AO is usually tied to the least significant bit of the address bus, for storing the HI-X74A output in two consecutive memory locations. (With AO low, the 8 MSBs only are enabled. With AO high, 4 MSBs are disabled, bits 4 through 7 are forced low, and the 4 LSBs are enabled). This two byte format is considered "left justified data," for which a decimal (or binary!) point is assumed to the left of byte 1:
BYTE 1 * X MSB X X X X X X X X X X BYTE 2 X LSB 0 0 0 0
Reading the Output Data
The output data buffers remain in a high impedance state until four conditions are met: R/C high, STS low, CE high and CS low. At that time, data lines become active according to the state of inputs 12/8 and AO . Timing constraints are illustrated in Figure 5. The 12/8 input will be tied high or low in most applications, though it is fully TTL/CMOS-compatible. With 12/8 high, all 12 output lines become active simultaneously, for interface to a 12-bit or 16-bit data bus. The AO input is ignored.
Further, AO may be toggled at any time without damage to the converter. Break-before-make action is guaranteed between the two data bytes, which assures that the outputs strapped together in Figure 6 will never be enabled at the same time. A read operation usually begins after the conversion is complete and STS is low. For earliest access to the data, however, the read should begin no later than (tDD + tHS) before STS goes low. See Figure 5.
CE CS tSSC
tHEC
CE CS tSSR tHSR
R/C
tSRC
tHSC R/C tSRR
tHRR
tHRC AO tSAC tHAC STS tDSC HIGH IMPEDANCE DB11-DB0 tC DB11-DB0 STS AO
tSAR
tHAR
tHS DATA VALID
tHD
HIGH IMPEDANCE tDD
tHL
See HI-X74A Timing Specifications for more information. FIGURE 3. CONVERT START TIMING
See HI-X74A Timing Specifications for more information. FIGURE 4. READ CYCLE TIMING
12
HI-574A, HI-674A
AO
ADDRESS BUS
1 2 12/8 3 4 AO 5 6 7 8 9 10 11 12 13 14 HI-X74A
STS 28 DB11 (MSB) 27 26 25 24 23 22 21 20 19 18 17 DB0 (LSB) 16 DIG. 15 COM. DATA BUS
FIGURE 5. INTERFACE TO AN 8-BIT DATA BUS
NIBBLE B ZERO OVERRIDE NIBBLE A, B
INPUT BUFFERS 12/8
NIBBLE C
CS
READ CONTROL
AO
STATUS
R/C
CE EOC9 CK D Q Q AO LATCH EOC13
CONVERT CONTROL
CURRENT CONTROLLED OSCILLATOR
STROBE CLOCK
POWER UP RESET
RESET
FIGURE 6. HI-X74A CONTROL LOGIC
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HI-574A, HI-674A
tHRL R/C
tDS STS tHDR tC tHS DATA VALID
DB11-DB0
DATA VALID
FIGURE 7. LOW PULSE FOR R/C - OUTPUTS ENABLED AFTER CONVERSION
R/C tHRH tDS
STS tC
tDDR
tHDR
DB11-DB0
HIGH-Z
DATA VALID
HIGH-Z
FIGURE 8. HIGH PULSE FOR R/C - OUTPUTS ENABLED WHILE R/C HIGH, OTHERWISE HIGH-Z
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HI-574A, HI-674A Die Characteristics
DIE DIMENSIONS: Analog: 3070mm x 4610mm Digital: 1900mm x 4510mm METALLIZATION: Digital Type: Nitrox Thickness: 10kA 2kA Metal 1: AlSiCu Thickness: 8kA 1kA Metal 2: AlSiCu Thickness: 16kA 2kA Analog Type: Al Thickness: 16kA 2kA PASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kA 0.5kA Silox Thickness: 12kA 1.5kA WORST CASE CURRENT DENSITY: 1.3 x 105 A/cm 2
Metallization Mask Layout
HI-574A, HI-674A
VLOGIC VLOGIC 12/8 DB11 AO CS STS
R/C DB10 CE VCC VREFOUT ANALOG COMMON DB8 DB9
ANALOG COMMON
DB7
ANALOG COMMON VREFIN
DB6
DB5
DB4 DB3
DB2 VEE DIGITAL COMMON DB0 BIPOLAR OFFSET 10V IN 20V IN DB1
15
HI-574A, HI-674A Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 -A-DBASE METAL b1 M (b) SECTION A-A (c) LEAD FINISH
D28.6 MIL-STD-1835 CDIP2-T28 (D-10, CONFIGURATION C) 28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
INCHES SYMBOL A b b1 b2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.232 0.026 0.023 0.065 0.045 0.018 0.015 1.490 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.92 0.66 0.58 1.65 1.14 0.46 0.38 37.85 15.49 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 5/18/94
E M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b AA C A-B S D S2 -CQ A L DS
b3 c c1 eA e eA/2
c
D E e eA eA/2 L Q S1 S2
0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 0.005 90o 28 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 0.13 90o 28 5.08 1.52 105o 0.38 0.76 0.25 0.038
ccc M C A - B S D S
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH.
aaa bbb ccc M N
16
HI-574A, HI-674A Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E28.6 (JEDEC MS-011-AB ISSUE B) 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 1 12/00
MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485
MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580
A
E A2 L A C L
-AD BASE PLANE -CSEATING PLANE D1 B1 B D1 A1
A1 A2 B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
0.010 (0.25) M C A B S
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.600 BSC 0.115 28 0.700 0.200
2.54 BSC 15.24 BSC 2.93 28 17.78 5.08
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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